1. Field of the Invention
The present invention relates to a magnetic disk apparatus having a hard disk controller (HDC) for controlling the data transfer and the processing of commands from a host system and a command processing method thereof.
2. Description of the Related Art
This type of magnetic disk apparatus which is well known in the art is widely used as an external storage device of a computer. In the magnetic disk apparatus, data recording (writing) or readout is effected by driving the magnetic head to effect the seeking operation in a radial direction of a rotating magnetic disk (which is hereinafter referred to as a medium) of a circular form.
A read command or write command for the magnetic disk apparatus is issued from a host system (computer). The issued command is supplied to a hard disk controller (HDC) in the magnetic disk apparatus. The HDC holds an access address of the command, that is, an address specified by the issued command is accessed. At the time of the end of the command, the access address is up-dated to a next sequential address value and then held.
After this, if a new different read command or write command is issued and the access address of the newly issued command coincides with the above held address, it is determined by the HDC that the access is sequential. As a result, it becomes possible to perform the automatic command execution (including data transfer) without using a firmware (FW). That is, the operation speed of command execution performed when the same commands are continuously issued for the sequential addresses can be enhanced. The above-mentioned speed enhancing method is generally referred to as a sequential cache function.
The sequential cache function is concretely explained. For example, in the read operation, a read command is first issued by the host system and the read operation for the medium is started. Data stored in the medium is read out by the read operation and stored into a buffer RAM. Then, after the operation of fetching all the target data is completed, data of the sequential addresses is continuously read out (prefetching).
Read data prefetched in response to the command issued from the host for the sequential addresses and stored in the buffer RAM can be continuously transferred. Therefore, a read command can be executed at high speed.
However, the sequential cache function in the above-described conventional disk unit has the following problems.
The address held by the HDC at the time of completion of the directly preceding command is erased when a different command is issued. That is, a new address is overwritten on the address storage area. Therefore, if a write command is executed once while a plurality of read commands are sequentially processed by the HDC, the address held at the time of completion of the final read command is erased and the write command is newly held. As a result, if the read access to the sequential addresses is executed again after completion of the write command, whether the addresses are sequential or not cannot be determined even if read data obtained by the cache operation is stored in the buffer RAM.
Therefore, the sequential cache function cannot be effectively carried out and the read operation with respect to the medium must be newly started again. Thus, a problem that the execution time for the command is greatly increased occurs.
Even when a sequence of access addresses are not completely continuous and if data is already transferred to the buffer RAM by prefetching in a case where a certain address and a next address are relatively close to each other, for example, the cache operation for the issuance of a command for an address which is not continuous is performed by using part of the data.
That is, since the automatic operation by the HDC cannot be performed in the operation of issuing a read command for the address which is not continuous, the command is executed by use of the FW. At this time, if the preceding access end address and the present access address are relatively close to each other, the command execution (data transfer) can be performed at high speed by the management of buffer RAM data by use of the FW because the data is already read out into the buffer RAM or is immediately read out after this.
Further, in a case where data read out by the execution of the read command previously performed is left in the buffer RAM and if a read command is issued to the address area again, the command execution can be immediately performed without effecting the operation of reading data from the medium.
Even in the above case, the following problem occurs. That is, as described before, if a write command is executed at least once during executions of read commands, it becomes necessary to check whether read data in the buffer RAM is changed or not. That is, whether or not the address range of data rewritten by the write command is contained in the address range of read data left in the buffer RAM is checked. However, as described before, the address held at the time of completion of a plurality of sequential write commands executed between the read commands is erased by issuance of a next read command. As a result, the address range of written data is made unclear and read data in the buffer RAM must be discarded, thereby making it impossible to efficiently perform the sequential cache. Therefore, the execution time of commands is greatly increased.